********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Sep 29, 2014
*ECN S14-1953, Rev. C
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si2328DS 4 1 2
M1  3 1 2 2 NMOS W=316673u L=0.25u   
M2  2 1 2 4 PMOS W=316673u L=0.50u  
R1  4 3     RTEMP 10E-2
CGS 1 2     140E-12
DBD 2 4     DBD
**************************************************************** 
.MODEL  NMOS       NMOS ( LEVEL  = 3            TOX    = 10E-8
+ RS     = 10E-2          RD     = 0            NSUB   = 2E17  
+ KP     = 3E-5           UO     = 650             
+ VMAX   = 0              XJ     = 5E-7         KAPPA  = 2E-1
+ ETA    = 1E-4           TPG    = 1  
+ IS     = 0              LD     = 0               
+ CGSO   = 0              CGDO   = 0            CGBO   = 0 
+ TLEV   = 1              BEX    = -1.5         TCV    = 6.2E-3
+ NFS    = 0.8E12         DELTA  = 0.1)
**************************************************************** 
.MODEL  PMOS       PMOS ( LEVEL  = 3            TOX    = 10E-8
+NSUB    = 5E16           TPG    = -1)   
**************************************************************** 
.MODEL DBD D (CJO=50E-12 VJ=0.38 M=0.30
+RS=0.1 FC=0.5 IS=1E-12 TT=5E-8 N=1 BV=100.2)
**************************************************************** 
.MODEL RTEMP R (TC1=11E-3 TC2=5.5E-6)
**************************************************************** 
.ENDS

